1. Technical Field
The present invention relates generally to a memory apparatus, and more particularly, to a non-volatile memory apparatus and a refresh method thereof.
2. Related Art
A memory apparatus such as a NAND flash memory includes a memory cell array, a page buffer circuit, and a control logic circuit for controlling the memory cell array and the page buffer circuit.
A memory cell array includes a plurality of strings. And each string includes a series of memory cells connected to each other with transistors formed at the ends. The memory cells of the plurality of strings are electrically connected through word lines, and each string is electrically connected to the page buffer circuit for sensing data through bit lines.
The control logic circuit controls the memory cell array and the operation of the page buffer circuit described above.
A page buffer circuit includes a plurality of latch circuits. A page buffer circuit can program a latched data to a memory cell connected to a selected bit line or perform a data read operation by loading and outputting of the data stored in a memory cell, which is connected to a selected bit line, to a latch.
A latch circuit in a page buffer circuit as described above may include a main latch unit having a general latch and a sub-latch unit having a dynamic latch. The general latch of the main latch unit may provide adequate data retention and driving force but hinders the efforts to achieve a high degree of device integration. The dynamic latch of the sub-latch unit is more suitable for achieving a high degree of integration than the general latch but exhibits poor data retention and driving force characteristics. For this reason, it is necessary to periodically perform a refresh operation in a dynamic latch. The number of sub-latch units may vary depending on the programming method, such as a single level cell (SLC) method, a multi-level cell (MLC) method, etc., implemented in the flash memory apparatus.
For performing the refresh operation on the sub-latch unit having the dynamic latch as described above, a signal is generated in the predetermined units of a logic control unit.
Generating the signal to perform the sub-latch unit refresh operation on the sub-latch unit imposes a burden on the logic control unit. Furthermore, when the refresh operation is performed only in the predetermined units of the logic control unit, it may delay an operation time.